1. Field of the Disclosure
The present disclosure relates to semiconductor devices, and more particularly to a semiconductor device comprising an integrator system.
2. Description of the Related Art
Traditional single-sampling sigma-delta modulators sample on one clock phase and integrate on the other. Since the differential amplifiers associated with the integrators of single-sampling sigma-delta modulators are only active during the integration phase, both bandwidth and power are wasted when the differential amplifiers are idle during the sampling phase. Better efficiency is obtained with double-sampling sigma-delta modulators, where sampling and integrating occur simultaneously on both phases of the clock. However, known double-sampling sigma-delta modulators suffer from either capacitor mismatch, resulting in additional quantization noise in the signal band, or hysteresis, resulting in a reduction of Signal to Noise Ratio (SNR).
A method and device reducing the affects of capacitor mismatch and reducing hysteresis would be useful.